(1) Field of the Invention
The present invention relates to manufacturing of semiconductor devices in general, and in particular, to a combined method of fabricating embedded flash memory cells having salicide and self-aligned contact structures.
(2) Description of the Related Art
Very large scale integration (VLSI) and more recently, the ultra scale integration (ULSI) of integrated circuits require semiconductor contact structures that provide high levels of performance. It is well known that in the progression of integrated circuits, as transistor dimensions approached the sub-micron regime, the conventional contacts used up to that point began to limit device performance in several ways. First, it was not possible to minimize the contact resistance when the contact hole was also scaled down for the contact resistance went up inversely with the smaller contact area. In addition, the area of the source/drain regions could not be minimized because the contact hole had to be aligned to these regions with a separate masking step, and extra regions had to be allocated for misalignment. The larger regions also resulted in increased course/drain-to-substrate junction capacitance, which slowed down the device speed. As a result, methods had to be developed to reduce the contact resistance while at the same time minimizing the contact areas commensurate with the large scale integration technology.
One such method used for logic devices is the salicide process and another related process called SAC, or self-aligned contact, is used for memory devices, which are described below. However, salicide and SAC processes are conventionally incompatible when used on the same VLSI or ULSI chip where both logic and memory devices are formed. For example, a dynamic random access memory (DRAM) or nonvolatile electrically programmable read only memory (EEPROM), or other similar memory devices are composed of an array of memory cells for storing digital information, while the peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers. It is disclosed later in the embodiments of this invention a method of using a combined process of salicide and SAC in order to affect scaling down of integrated circuit technology without the attendant redundant masking and other steps that are currently employed.
A conventional self-alignment technique used in forming a typical device is illustrated in FIG. 1. In FIG. 1, gate (40) is formed on an insulator oxide (30) which in turn is formed on a silicon substrate (10) having source/drain regions (20) delineated by field oxide regions (50). The section of the substrate between the source/drain regions (20) is called the channel region (15). The device becomes operational when a voltage V.sub.g, larger than a threshold voltage, V.sub.th, is impressed on gate (40) through a conductive path such that current flows between source and drain regions (20) through channel (15). The source and drain are also connected by means of their own conductive paths (67) to complete the integrated circuit. The conductive paths are interconnections that are fabricated by depositing metal into holes that are formed in interlevel dielectric layer (60) as shown in FIG. 1. It will be shown later that the self-aligned contacts (SACs) in those holes are formed by employing a self-alignment technique.
The physical structure and the electrical characteristics of gate electrode (40) have a controlling effect on the operation of the device. Its forming is usually complex and requires exacting processes. Furthermore, materials used for the gate must be compatible with processes that follow up to the completion of the manufacture of the semiconductor devices. With the advent of ULSI (ultra large scale integration) of devices, the shrinking dimensions of the gate as well as the materials used to form the gates have gained even more significance. Thus, if aluminum were to be used as the gate material for example, then, because of its low melting point, it would have to be deposited following the completion of all high-temperature process steps, including drive-in of the source and drain regions. To form the gate electrode in proper relationship to the source/drain, it must be separately aligned with respect to the source and drain. This alignment process adversely affects both packing density and parasitic overlay capacitances between the gate and source/drain regions. For these reasons, it has become a recent practice to use polycrystalline silicon (poly-Si), which has the same high melting point as the silicon substrate, as the gate material. Hence, polysilicon can now be deposited over the gate to form the gate electrode prior to the source and drain formation. Consequently, the gate itself can serve as a mask during formation of the source and drain regions by either diffusion or ion implantation, as is known in the art. Gate (40) thereby becomes nearly perfectly aligned over channel (15) and with respect to source/drain (20) shown in FIG. 1. The only overlap of the source and drain is due to lateral diffusion of the dopant atoms. This self-alignment feature simplifies the fabrication sequence, increases packing density, and reduces the gate-source and gate-drain parasitic overlap capacitances. For completeness, we note that the threshold voltage, V.sub.th, of MOS device is also favorably affected by the use of polysilicon as the gate electrode material.
On the other hand, polysilicon has much higher electrical resistance as compared to aluminum, for example, and the miniaturization of devices in the ULSI era has exacerbated the electrical properties of the poly-Si gate electrode. Polysilicon is commonly doped by ion implantation to lower the resistivity substantially. However, according to Wolf in his book "Silicon Processing for the VLSI Era," vol. 1, Lattice Press, Sunset Beach, Calif., 1986, pp. "176-77", even at the highest dopant concentrations, a 0.5 micrometer (.mu.m)-thick polysilicon film has a sheet resistance of about 20.OMEGA./sq which is about two orders of magnitude larger than that of aluminum film of the same thickness. The resulting high values of line resistance can lead to long propagation delays and severe dc voltage variations within an ULSI circuit.
In order to overcome the high resistivity problem encountered with polysilicon alone, polycides, a multilayer structure comprising polysilicon (42) and metal silicides (44), are used to form gate electrodes (40) such as depicted in FIG. 1. Silicides are a group of refractory metal compounds (MSi.sub.x) that are formed by basically three techniques, each of which involves deposition followed by a thermal step to form the silicide: 1) deposition of a pure metal such as tungsten (W), titanium (Ti) or Molybdenum (Mo) on polysilicon, 2) simultaneous evaporation of the silicon and the refractory metal from two sources, and 3) sputter-depositing the silicide itself from a composite target, or by co-sputtering or layering.
In a salicide process, after the polysilicon layer (42) has been deposited and patterned following conventional lithographic and etching methods, sidewall spacers (75) are formed. This is accomplished by depositing a layer of oxide (not shown) which conformally covers the polysilicon layer (42). The oxide layer is then etched back anisotropically until the polysilicon layer is exposed. Unetched portions of the oxide at the vertical sides of the poly-Si remain following this etch. These residual structures then form the oxide spacers (75) shown in FIG. 1. As is well known in the art, the purpose of the spacers is to prevent shorting between metal deposited subsequently on the gate and on the source/drain regions. The metal used to form the silicide (44) is deposited. Substrate (10) is next heated, which causes the silicide reaction to occur wherever the metal is in contact with the silicon. Everywhere else, the metal remains untreated. The unreacted metal at places such as over the spacers is selectively removed through the use of an etchant that does not attack the silicide, the silicon substrate, or the oxide. As a result, in addition to the polysilicon layer (42), only each exposed source and region is now completely covered by silicide film (44) but no other place. It will be noted that the resulting multilayered polycide film over the gate comprising polysilicon and silicide has been self-aligned with respect to the source/drain regions and the combination is accordingly called a self-aligned silicide or, a salicide. A dielectric layer is next deposited onto the salicide, and holes are opened in it down to the salicide layer. Metal is deposited into the holes to make contacts (67) with the salicide.
It will be appreciated by those skilled in the art that the oxide spacers can also be used in memory cells for self-aligning source/drain regions without the need for additional photolithographic step. This is shown in a conventional memory cell of FIG. 2 where a first polysilicon floating gate (45) and second polysilicon control gate (90) have been formed following methods known in the art. The floating gate and the control gate are separated by an intervening interpoly oxide (80). Subsequent to the forming of the gates, oxide spacers (85) are also formed as shown in FIG. 2. The source/drain regions are then formed by ion implantation without the use of a lithography step. The spacer and the field oxide act as masks to prevent the ion implantation from penetrating to the silicon substrate below. Therefore, only the active regions covered by the gate oxide, layer (35) in FIG. 2, are implanted, and hence, the source and drain are self-aligned with respect to the stacked gates, (45), (90), and contact hole (63).
Thus, prior art provides methods of forming salicides and SACs, but with separate and non-integrated steps. The present invention discloses a process where the two methods can be combined advantageously. In addition, and as a by-product, an improved method of forming dual-gate oxide is also disclosed. Here, in order to optimize the performance of memory devices and logic devices on the same integrated chip, it is desirable to provide different thicknesses of the gate oxide for the different types of devices. Typically, a thin gate oxide is used in the peripheral logic circuits to enhance FET device performance, while it is desirable to provide a thicker gate oxide for the higher gate voltage requirement on the on the access transistors of a memory cell. A dual gate oxide is obtained by thermally growing in the memory cell device area and in the logic device area (peripheral area) a first gate oxide on the substrate having a field oxide. A photoresist mask is then used to mask the gate oxide over the memory cell device area, and the gate oxide is etched in the logic device area. The photoresist is then stripped and a second gate oxide is grown on the logic device are while the original gate oxide in the memory cell device area increases in thickness. Unfortunately, though, by the method of the prior art, the presence of the photoresist over the gate oxide in the memory device area contaminates the oxide and degrades the device electrical characteristics. This problem is also alleviated with the disclosed method of this invention.
Fang, et al., of U.S. Pat. No. 5,668,035 avoids the problem of contamination mentioned above by not directly applying the photoresist onto the gate oxide. Jeong-Gyoo in U.S. Pat. No. 5,155,056 discloses a process for forming a cell having a self-aligned capacitor contact and a structure thereof. Lai of U.S. Pat. No. 5,229,311 teaches a method of reducing the degradation effects associated with avalanche injection or tunneling of hot-electrons in a field-effect semiconductor device. The present invention teaches a combined method of forming salicide and SAC structures together while, at the same time, providing a dual gate oxide.